verilog 硬體描述語言

module top();

wire a,b;
reg c;



system_clock #50 clock_1(a);

system_clock #100 clock_2(b);

always
#1 c=a&b;// and (c,a,b);

endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
always@(posedge clk)if($time>1000) #(PERIOD-1) $stop;
endmodule