12/28 verilog上機考試

module top;
system_clock #50 c1(d);
system_clock #100 c2(c);
system_clock #200 c3(b);
system_clock #400 c4(a);
number a1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a1,c1,d);
and(w3,b,d);
and(w4,a,b1,c,d1);
or(e,w1,w2,w3,w4);
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2) clk=~clk;
always@(posedge clk)
if($time>10000)
$stop;
endmodule