11/16 四個輸入and閘

module and4_algo(y_out,x_in);
input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always @ (x_in)
begin:and_loop
y_out=1;
for(k=0;k<=3;k=k+1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule

11/09 未完成

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule
module and4_rtl(y_out,x_in);
input [3:0] x_in;
out y_out;
assign y_out=&x_in;
endmodule