12/28 verilog上機考試

module top;
system_clock #50 c1(d);
system_clock #100 c2(c);
system_clock #200 c3(b);
system_clock #400 c4(a);
number a1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b,c1);
and(w2,a1,c1,d);
and(w3,b,d);
and(w4,a,b1,c,d1);
or(e,w1,w2,w3,w4);
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2) clk=~clk;
always@(posedge clk)
if($time>10000)
$stop;
endmodule

RTL 含時脈周期1

module top();

wire y_out,x_in1,x_in2,x_in3,x_in4;

system_clock #100 clock_1(x_in1);
system_clock #200 clock_2(x_in2);
system_clock #400 clock_3(x_in3);
system_clock #800 clock_4(x_in4);

and4_rtl X1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;reg clk;
initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
always@(posedge clk)if($time>10000) #(PERIOD-1) $stop;
endmodule

verilog 硬體描述語言

module top();

wire a,b;
reg c;



system_clock #50 clock_1(a);

system_clock #100 clock_2(b);

always
#1 c=a&b;// and (c,a,b);

endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
always@(posedge clk)if($time>1000) #(PERIOD-1) $stop;
endmodule