RTL 含時脈周期1

module top();

wire y_out,x_in1,x_in2,x_in3,x_in4;

system_clock #100 clock_1(x_in1);
system_clock #200 clock_2(x_in2);
system_clock #400 clock_3(x_in3);
system_clock #800 clock_4(x_in4);

and4_rtl X1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;reg clk;
initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
always@(posedge clk)if($time>10000) #(PERIOD-1) $stop;
endmodule