10/26 二位元比較器 報告 方法一

verilog二進位器方法一:
module compare_2a(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
wire A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B=A1&(~B1)A0&(~A0)&(~B0)(~A0)&B1&B0;
assign A_eq_B=(~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&B0A1&A0&B1&B0A1&(~A0)&B1&(~B0);
endmodule

10/26 二位元比較器 含時脈波器

module top();

wire A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0;

system_clock #100 clock_1(A1);
system_clock #200 clock_2(A0);
system_clock #400 clock_3(B1);
system_clock #800 clock_4(B0);

compare_2a X1(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);

endmodule

module compare_2a(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
wire A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=(~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B=A1&(~B1)A0&(~A0)&(~B0)(~A0)&B1&B0;
assign A_eq_B=(~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&B0A1&A0&B1&B0A1&(~A0)&B1&(~B0);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;
always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end
always@(posedge clk)if($time>10000) #(PERIOD-1) $stop;
endmodule

10/26 二位元比較器報告 方法二

verilog報告:第二部分
module compare_2c(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0]A,B;
output A_lt_B,A_gt_B,A_eq_B;
reg A_lt_B,A_gt_B,A_eq_B;
always @(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if (A==B)A_eq_B=1;
else if (A>B)A_gt_B=1;
else if (A