11/09 未完成

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule
module and4_rtl(y_out,x_in);
input [3:0] x_in;
out y_out;
assign y_out=&x_in;
endmodule